This invention relates generally to pulse code apparatus and in particular to a pulse code sequence analyzer system and method for determining the quality of data transmission in data transmission systems.
Transmission systems generally have transmitter/receiver apparatus and a transmission facility interconnecting the transmitter/receiver apparatus and providing a path over which data may be exchanged between the transmitter/receiver apparatus. Increasing advances in technology and the need to exchange information in a short time interval require greater speed in the rate of transmitting data. The technology has gone from analog systems to digital information systems capable of transmitting digital information in the form of xe2x80x9c0""sxe2x80x9d and xe2x80x9c1""sxe2x80x9d oftentimes referred to as bits. In an effort to increase the speed of transmission systems, the technology has advanced to the use of optical transmission systems using optical transmitter/receivers interconnected by optical transmission facilities such as optical fibers or laser systems that transmit optical pulse bit information between the optical transmitter/receivers.
Digital and optical transmission systems oftentimes have transmitter/receiver devices connected by transmission facilities all of which are subject to noise wherein noise may be any spurious or undesired disturbances that tend to disrupt the transmitted data by generating errors that obscure and mask the data information. During the design phase of the system special efforts are undertaken to design the apparatus to minimize noise. However, erratic disturbances normally beyond control of the designer, occur irregularly due to spontaneous fluctuations. These types of disturbances may be electromagnetic inferences, power supply problems, electrical storms, surges in voltages and the like.
Various techniques have been devised to measure errors and noise in communication and transmission systems. In some apparatus, data and a clock signal recovered from the data is applied to an error corrector and to a delay. A comparator compares the corrected data with the delayed data and outputs a pulse when the data are not coincident. The recovered clock signal is counted and when a predetermined number are counted, the apparatus latches the comparator generated pulses to obtain a received data bit error sum approximate number. In some apparatus, a sliding window is used wherein the number of error bits received during a predetermined number of received bits is calculated to determine the bit error rate. In yet other systems, the bit error rate is monitored by integrating line bit-interleaved-parity indications over a length of time and sounding an alarm when the count exceeds a threshold.
Although apparatus has been previously disclosed for determining the bit error rate, the increasing need for faster transmission of information requires the development of apparatus and a method of improving the determination of noise and errors rates occurring in the transmitter/receivers and occurring during transmission of data over transmission facilities interconnecting the transmitter/receivers.
It is an object of the invention to provide pulse code sequence apparatus and a method for determining errors occurring in transmitters and receivers and in data transmission between the transmitters/receivers.
It is also an object of the invention to provide pulse code sequence apparatus having a data converter for receiving the data and a clock section for recovering a clock signal from the received data and for dividing the recovered clock into a pair of subtone clock signals.
It is also an object of the invention to provide the data converter with a reference and an auxiliary channel and to couple ones of the clock section divided subtone clock signals to the reference and auxiliary channels.
It is also an object of the invention to insert a fixed and variable time delay into one of the subtone clock signals and connect the one time delayed subtone clock signal to the data converter reference channel and to insert a variable time delay into the other subtone clock signal and apply the other subtone clock signal to the data converter auxiliary channel.
It is also an object of the invention to provide a processor for controlling a length of a variable time delay inserted into the subtone clock signals and apply the delayed subtone clock signal to the reference and auxiliary channels to create a time delay between the reference and auxiliary channels in which to detect errors occurring in the pulse code sequence analyzer received data transmissions.
It is also an object of the invention to provide a processor controlled voltage comparator input for the pulse code sequence data converter reference and auxiliary channel to determine the voltage level of data received by the channels.
It is a further object of the invention to provide a counter for counting the errors detected during the processor controlled time delay between the data converter reference and auxiliary channels and for enabling the processor to create a matrix of counted errors in a varying voltage versus varying time format enabling the processor to determine a probability predicting the data errors.
In a preferred embodiment of the invention, a pulse code sequence analyzer for analyzing data has a data converter for receiving the data and clock front end apparatus for recovering a clock signal from the data and applying generated subtone clock signals to the data converter. A ripple counter coupled with the data converter and the clock front end apparatus records errors occurring in the data. A processor coupled to the counter, data converter and clock means controls the clock and data converter means to detect errors occurring in the data received by the data converter means and records an error matrix determining a probability predicting errors occurring in the data.
Also in accordance with the preferred embodiment of the invention, the pulse code sequence analyzer for analyzing data has a data converter with a reference and an auxiliary channel for receiving the data and with each channel having a processor controlled voltage comparator for determining a variable voltage level of data received by the reference and auxiliary channel.
Also in accordance with the preferred embodiment of the invention, the pulse code sequence analyzer for analyzing data has clock front end buffer means for dividing the recovered clock signal into a pair of subtone clock signals, a fixed delay line for inserting a fixed time delay into a first one of the subtone clock signals and a pair of variable delay lines controlled by a processor for inserting a variable time delay into the one subtone clock signal following the fixed time delay and a variable time delay into the other subtone clock and applying the time delayed clock signals to the data converter reference and auxiliary channels.
Also in accordance with the preferred embodiment of the invention, the pulse code sequence analyzer for analyzing data has a processor controlling the variable delay lines to insert variable time delays into subtone clock signals and apply the time delayed subtone clock signals to the data converter reference and auxiliary channels to create a time delay between the reference and auxiliary channels in which to detect errors occurring in the pulse code sequence analyzer received data transmissions.
Also in accordance with the preferred embodiment of the invention, the pulse code sequence analyzer for analyzing data has a counter apparatus connected to the data converter reference and auxiliary channels for counting errors detected during the processor controlled time delay between the data converter reference and auxiliary channels and for enabling the processor to create a matrix of counted errors enabling the processor to determine a probability predecting the transmitted data.
Also in accordance with the preferred embodiment of the invention, a method of analyzing data in a data transmission has the steps of receiving data from transmitter/receivers and a transmission path interconnecting the transmitter/receivers in voltage comparators of a reference and auxiliary channel and recovering a clock signal from the received data. The method further includes the steps of dividing the recovered clock signal by a predefined number N and generating a pair of subtone clock signals. The method continues by inserting a fixed length time delay and a variable time delay in a subtone signal and applying the subtone signal to the reference channel and by inserting another variable time delay in the other subtone clock signal applied to the auxiliary channel wherein the subtone clock signals are separated by a variable time delay. Method steps include varying the voltage level of the channel voltage regulators and the length of the variable time delays in time thereby changing the time length of the channel separating variable time delay. The method continues by detecting and counting errors appearing in the received data during the variable time delay and recording the counted errors in a memory of a processor as a matrix of the counted errors in voltage amplitude versus time thereby enabling the processor to determine a probability predicting the data errors. A step of varying the voltage level of the channel voltage regulators and the length of the variable time delays includes a step of generating analog signals in response to digital signals received from the processor for controlling the voltage level of the channel voltage comparators and the time delay of the variable time delays in real time.